This disclosure relates generally to the field of computing systems, and more particularly to slew rate control in a computing system.
Electrical devices such as processors, memory controllers, and graphics controllers are part of many computer and electronic systems. A typical electrical system has drivers to drive signals from one device to another device. Drivers are often designed to drive signals with a specific slew rate (i.e., edge steepness), which is the rate at which the signal switches between different signal levels within a specified time. A relatively high slew rate may introduce undesirable noise into a signal, while a relatively low slew rate may lengthen the time needed for the signal to switch between the signal levels, limiting the operating frequency of the system.
Phase rotators are computing system components that are designed to output a signal having a specified frequency and slew rate. The signal output by a phase rotator may be used to, for example, adjust the optimum sampling point in time and clock skew adjustments that are required for the burst mode data transmission. A computer system may include many phase rotators. A phase rotator may include three stages: a phase selector stage that selects two input phases from a plurality of input phases provided by a multiphase generator; a edge slewing stage that adjusts the slew rate of the two selected input phases from the phase selector stage, and a phase blending stage to interpolate between two slew rate adjusted input phases from the edge slewing stage to generate the phase rotator output signal with the desired phase and frequency. The phase rotator selects, adjusts, and interpolates between one of the even input phases and one of the adjacent odd phases from the plurality of input phases provided by the multiphase generator to generate the phase rotator output signal.
The edge slewing stage determines the performance of the phase rotator with respect to its phase linearity, which is measured in differential non-linearity (DNL) and integral non-linearity (INL). If the edges of the two interpolated phase signals are too steep (i.e., the slew rate is too high), there will be relatively high DNL values. If the edges of the interpolated phase signals are too flat (i.e., the slew rate is too low), the phase interpolation may cause poor INL, significant duty cycle distortion or even failure. It is therefore important to adjust the slew rate of the rising and falling edges to be identical, and to adjust the absolute value of the slew rate optimally such that the phase interpolation can be operated with minimum DNL and INL values. If timing jitter is neglected, the slew rate may be adjusted by the edge slewing stage such that the signals output by the edge slewing stage just hit the voltage rails, so that the signals output by the edge slewing stage allow the phase blending stage to operate relatively linearly. A safety margin might be added to the slew rate adjustment to prevent the signals from not hitting the voltage rails because of timing jitter. However, supply noise jitter may contribute to amplitude fluctuations in the phase rotator output signal.